View AT25F2048-14_9059150.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? 33 mhz clock rate ? byte mode and 256-byte page mode for program operations ? sector architecture: ? four sectors with 64k bytes each ? 256 pages per sector ? product identi fication mode ? low-voltage operation ? 2.7 (v cc = 2.7v to 3.6v) ? sector write protection ? protect 1/4, 1/2 or entire array ? write protect (wp ) pin and write disable instructions for both hardware and software data protection ? self-timed progr am cycle (30 s/byte typical) ? self-timed sector erase cycl e (1 second/sector typical) ? single cycle reprogramming (erase and program) for status register ? high reliability ? endurance: 10,000 write cycles typical ? data retention: 20 years ? 8-lead jedec soic and 8-lead ultra thin small array (sap) packages ? die sales: wafer form, tape and reel and bumped wafers description the at25f2048 provides 2,097,152 bits of serial reprogrammable flash memory organized as 262,144 words of 8 bits eac h. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the at25f2048 is available in a space-saving 8-lead jedec soic and ultra thin sap package. rev. 2455i?sflsh?5/07 2mbit high speed spi serial flash memory 2m (262,144 x 8) at25f2048 pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead ultra thin sap bottom view 8-lead soic
2 at25f2048 2455i?sflsh?5/07 the at25f2048 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all write cycles ar e completely self-timed. block write protection for top 1/ 4, top 1/2 or the entire memory array is enabled by pro- gramming the status register. separate write enable and write disable instructions are provided for additional data protection. hardwa re data protection is provided via the wp pin to protect against inadvertent write at tempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. figure 1. block diagram absolute maximum ratings* operating temperature.................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .....................................-1.0v to +3.6v maximum operating voltage ............................................ 4.2v dc output current........................................................ 5.0 ma 262,144 x 8
3 at25f2048 2455i?sflsh?5/07 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il and v ih max are reference only and are not tested. table 1. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +3.6v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v table 2. dc characteristics (prelimin ary ? subject to change) applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +2.7v to +3.6v, t ac = 0 c to +70 c, v cc = +2.7v to +3.6v (unless otherwise noted) symbol parameter test condition min typ max units v cc supply voltage 2.7 3.6 v i cc1 supply current v cc = 3.6v at 33 mhz, so = open read 10.0 17.0 ma i cc2 supply current v cc = 3.6v at 33 mhz, so = open write 25.0 45.0 ma i sb standby current v cc = 2.7v, cs = v cc 2.0 10.0 a i il input leakage v in = 0v to v cc -3.0 3.0 a i ol output leakage v in = 0v to v cc , t ac = 0 c to 70 c-3.0 3.0 a v il (1) input low voltage -0.6 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 2.7v v cc 3.6v i ol = 0.15 ma 0.2 v v oh output high voltage i oh = -100 av cc - 0.2 v
4 at25f2048 2455i?sflsh?5/07 notes: 1. the programming time for n bytes will be equal to n x t bpc . 2. this parameter is ensured by characterization at 3.0v, 25 c only. 3. one write cycle consists of erasing a sector, followed by programming the same sector. table 3. ac characteristics (preliminary ? subject to change) applicable over recommended operating range from t a = -40 c to +85 c, v cc = +2.7v to +3.6v c l = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter min typ max units f sck sck clock frequency 0 33 mhz t ri input rise time 20 ns t fi input fall time 20 ns t wh sck high time 9 ns t wl sck low time 9 ns t cs cs high time 25 ns t css cs setup time 25 ns t csh cs hold time 10 ns t su data in setup time 5 ns t h data in hold time 5 ns t hd hold setup time 15 ns t cd hold hold time 15 ns t v output valid 9ns t ho output hold time 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec erase cycle time per sector 1.0 s t sr status register write cycle time 60 ms t bpc byte program cycle time (1) 30 50 s endurance (2) 10k write cycles (3)
5 at25f2048 2455i?sflsh?5/07 serial interface description master: the device that generat es the serial clock. slave: because the serial clock pin (sck) is always an input, the at25f2048 always operates as a slave. transmitter/receiver: the at25f2048 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code t hat defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25f2048, and the serial output pin (so) wi ll remain in a high impedance state until the falling edge of cs is detected again. this will rein itialize the serial communication. chip select: the at25f2048 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25f2048. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial comm unication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the 25f2048 has a write lockout feature that can be activated by asserting the write protect pin (wp ). when the lockout feature is activated, locked-out sectors will be read only. the write protect pin will allow normal read/write operations when held high. when the wp is brought low and wpen bit is ?1?, all write operations to the status register are inhibited. wp going low while cs is still low will in terrupt a write to the status register. if the in ternal status register write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the at25f2048 in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ?1?.
6 at25f2048 2455i?sflsh?5/07 figure 2. spi serial interface master: microcontroller slave: at25f2048 data out (mosi) data in (miso) serial clock (spi ck) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs si so sck cs
7 at25f2048 2455i?sflsh?5/07 functional description the at25f2048 is designed to interface direct ly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the at25f2048 utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 4. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low transition. write is defined as program and/or erase in this specification. the following commands, program, sector erase, chip erase, and wrsr are write instructions for at25f2048. write enable (wren): the device will power up in the write disable state when v cc is applied. all write instructions must th erefore be preceded by the wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the wrdi instruction disables all writ e commands. the wrdi instruction is independent of the sta- tus of the wp pin. read status register (rdsr): the rdsr instruction prov ides access to the sta- tus register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. simila rly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. during internal write cycles, all other commands will be ignored except the rdsr instruction. table 4. instruction set for the at25f2048 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array program 0000 x010 program data into memory array sector erase 0101 x010 erase one sector in memory array chip erase 0110 x010 erase all sectors in memory array rdid 0001 x101 read manufacturer and product id table 5. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy
8 at25f2048 2455i?sflsh?5/07 read product id (rdid): the rdid instruction allows the user to read the manufac- turer and product id of the device. the fi rst byte after the instruction will be the manufacturer code (1fh = atmel), followed by the device code, 63h. write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection for the at25f2048. the at25f2048 is divided into four sectors where the top quarter (1/4), top half (1/2), or all of the memory sectors can be protected (locked out) from write. any of the locked-out sector s will therefore be read only. the locked-out sector and the correspond ing status register control bits are shown in table 7. the three bits, bp0, bp1, and wpen, are nonvolatile cells that have the same proper- ties and functions as the regu lar memory cells (e.g., wren, t wc , rdsr). table 6. read status register bit definition bit definition bit 0 (rdy ) bit 0 = 0 (rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1 = 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bp0) see table 7. bit 3 (bp1) see table 7. bits 4-6 are 0s when device is not in an internal write cycle. bit 7 (wpen) see table 8. bits 0-7 are 1s during an internal write cycle. table 7. block write protect bits level status register bits at25f2048 bp1 bp0 array addresses locked out locked-out sector(s) 0 0 0 none none 1(1/4) 0 1 030000 - 03ffff sector 4 2(1/2) 1 0 020000 - 03ffff sector 3, 4 3(all) 1 1 000000 - 03ffff all sectors (1 - 4)
9 at25f2048 2455i?sflsh?5/07 the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enabl e (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the wp pin is high or the wpen bit is ?0.? when the device is hard- ware write protected, writes to the status re gister, including the block protect bits and the wpen bit, and the locked-out sectors in the memory array are disabled. write is only allowed to sectors of the memory which are not locked out. the wrsr instruction is self-timed to automatically erase and program bp0, bp1, and wpen bits. in order to write the status register, the device must first be write en abled via the wren instruction. then, the instruction and data for the three bi ts are entered. during the internal write cycle, all instructions will be ignored ex cept rdsr instructions. the at25f2048 will automatically return to write disable st ate at the completion of the wrsr cycle. note: when the wpen bit is hardware write prot ected, it cannot be changed back to ?0?, as long as the wp pin is held low. read (read): reading the at25f2048 via the so (serial output) pin requires the fol- lowing sequence. after the cs line is pulled low to select a device, the read instruction is transmitted via the si line followed by the byte address to be read (refer to table 9). upon completion, any data on the si line will be ig nored. the data (d7-d0) at the speci- fied address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data co mes out. the read instruction can be contin- ued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is r eached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read instruction. program (program): in order to program the at25f2048, two separate instruc- tions must be executed. first, the devic e must be write enabled via the wren instruction. then the program instruction can be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field loca- tion selected by the block write protecti on level. during an internal self-timed programming cycle, all co mmands will be ignored exce pt the rdsr instruction. the program instruction requires the following sequence. after the cs line is pulled low to select the device, the program instruction is transmitted via the si line followed by the byte address and the data (d7-d0) to be programmed (refer to table 6). programming will start after the cs pin is brought high. the low-to-high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit for mode 0. the ready/busy status of the device can be determined by initiating a rdsr instruc- tion. if bit 0 = 1, the program cycle is still in progress. if bit 0 = 0, the program cycle has ended. only the rdsr instruction is enabled during the program cycle. table 8. wpen operation wpen wp wen protectedblocks unpr otectedblocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
10 at25f2048 2455i?sflsh?5/07 a single program instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. the starting byte coul d be anywhere within the page. when the end of the page is reache d, the address will wrap around to the beginn ing of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. if more th an 256 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. the same byte cannot be reprogrammed without erasing the whole sector first. the at25f2048 will automatic ally return to the write di sable state at the completion of the program cycle. note: if the device is not write enabled (wren), th e device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-initiate the serial communication. sector erase (sector erase): before a byte can be reprogrammed, the sector which contains the byte must be erased. in order to erase the at25f2048, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the sector er ase instruction can be executed. the sector erase instruction erases every byte in the selected sector if the sector is not locked out. sector address is automatically determined if any address within the sector is selected. the sector erase instruction is in ternally controlled; it will automatically be timed to completion. during this time, all commands will be ignored, except rdsr instruction. the at25f2048 will automatically return to the write disable state at the completion of the sector erase cycle. chip erase (chip erase): as an alternative to the sector erase, the chip erase instruction will erase every byte in all se ctors that are not locked out. first, the device must be write enabled via the wren instruct ion. then the chip erase instruction can be executed. the chip erase instruction is inte rnally controlled; it will automatically be timed to completion. the chip erase cycle time typically is 4 seconds. during the inter- nal erase cycle, all instructions will be ignored except rdsr. the at25f2048 will automatically return to the write disable stat e at the completion of the chip erase cycle. table 9. address key address at25f2048 a n a 17 - a 0 don?t care bits a 23 - a 18 table 10. sector addresses sector address at25f2048 sector 000000 to 00ffff sector 1 010000 to 01ffff sector 2 020000 to 02ffff sector 3 030000 to 03ffff sector 4
11 at25f2048 2455i?sflsh?5/07 timing diagrams (for spi mode 0 (0, 0)) figure 3. synchronous data timing figure 4. wren timing figure 5. wrdi timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
12 at25f2048 2455i?sflsh?5/07 figure 6. rdsr timing figure 7. wrsr timing figure 8. read timing cs s ck 01234567891011121314 si instruction so 76543210 data out msb high impedance 15 cs si s ck high impedance instruction 3-byte address 01234 4 5 5 6 6 7 7 8 9 10 11 28 23 22 21 3 ... 21 321 0 0 29 30 31 32 33 34 35 36 37 38 so 39
13 at25f2048 2455i?sflsh?5/07 figure 9. program timing figure 10. hold timing figure 11. sector erase timing cs sck si so 3-byte address 1st byte data-in 256th byte data-in instruction high impedance 0123456789101128 23 22 21 3 1 0 6 5 4 3 2 1 0 7 2 29 30 31 32 33 34 2075 2076 2078 2077 2079 s o s ck hold t cd t hd t hz t lz t cd t hd c s x x = don?t care bit
14 at25f2048 2455i?sflsh?5/07 figure 12. chip erase timing figure 13. rdid timing x x = don?t care bit 12 13 14 15 16 17 18 19 x manufacturer code (atmel) device code
15 at25f2048 2455i?sflsh?5/07 note: 1. available in tape and reel and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact serial interface marketing. ordering information ordering code voltage package operation range at25f2048n-10su-2.7 at25f2048y7-yh27-t (nipdau lead finish) 2.7 8s1 8y7 lead-free/halogen-free/ industrial temperature (-40 c to 85 c) 2.7 at25f2048-w27-11 (1) 2.7 die sale industrial temperature (-40 c to 85 c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline pack age (jedec soic) 8y7 8-lead, 6.00 mm x 4.90 mm body, ultra thin, dual footprint, non-leaded, small array package (sap) options -2.7 low voltage (2.7v to 3.6v)
16 at25f2048 2455i?sflsh?5/07 package information 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at25f2048 2455i?sflsh?5/07 8y7 - sap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y7 , 8-lead (6.00 x 4.90 mm body) ultra-thin soic array package (utsap) y7 b 8y7 10/13/05 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 0.60 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 3.30 3.40 3.50 e1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
18 at25f2048 2455i?sflsh?5/07 revision history rev. no. date comments 2455i 5/2007 added die sale product offering 2455h 4/2007 changed operation range description added ?nipdau lead finish? to at25f2048y7-yh27-t part number 2455g 3/2007 implemented revision history added sap package removed preliminary
printed on recycled paper. 2455i?sflsh?5/07 disclaimer: the information in this document is provided in connection with atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseq uential, punitive, special or i nciden- tal damages (including, without limitation, dam ages for loss of profits, business inte rruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of th is document and reserves the rig ht to make changes to specifications and product descriptions at any time withou t notice. atmel does not make any commitm ent to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ?2007 atmel corporation . all rights reserved. atmel ? logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other te rms and product names may be trademarks of others.

▲Up To Search▲

Price & Availability of AT25F2048-14

	To Download AT25F2048-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .